1. Field
This disclosure relates generally to semiconductor processing, and more specifically, to a method for forming a split-gate memory.
2. Related Art
A split-gate non-volatile memory cell includes a control gate and a select gate for controlling program, erase, and read operations. The control gate is used to control programming and erasing of the memory cell while the select gate is used to select when a memory cell is programmed or read. A prior art manufacturing process uses a three mask lithography process to form the two gates. Other processes may include the use of sacrificial features in addition to the three lithography processes. Alignment of each of the three masks is important. Any misalignment can cause uncontrolled select gate length and control gate length, which may result in variations in threshold voltage (VT) and leakage current as well as degraded manufacturing yield. One prior art split-gate memory cell includes two polysilicon layers, where a portion of one polysilicon layer overlaps with a portion of the other layer. Any misalignment in the masks used to form the select and control gates may require etching through different polysilicon thicknesses on either side of the split-gate memory cells, resulting in either under etching or over etching the polysilicon. In addition, the use of a three mask lithography process increases costs because of repeated steps and increased manufacturing time.
Therefore, what is needed is a method for forming a split-gate memory cell that solves the above problems.